ARM Cortex-M4 Assembly Coding

Inline assembly code is used to write pure assembly code within C programming language code to access processor core registers. To use inline assembly, the compiler's assembly syntax must be followed.

An example of an inline assembly statement is:

__asm volatile("MOV R0, R1");

Inline assembly can be used to move the content of a C programming language variable to an ARM register or vice versa. For example, it can be employed to transfer the content of a control register to a C variable.

For further examples of inline assembly code, please refer to the following GitHub link.

Link to the code in github: https://github.com/MusaabTaha/STM32-ARM-Cortex-M4-Microcontroller-Codes/blob/main/inlineAssembly.c

Written By: Musaab Taha

Arm Cortex-M4 Processor Registers

The Arm Cortex-M4 registers are integral components located within the processor core. It comprises 13 general-purpose registers, R0 through R12. All core registers are 32-bit wide. The stack pointer (SP) is further divided into the Process Stack Pointer (PSP) and the Main Stack Pointer (MSP) based on the processor's active mode. The Link Register (LR), R14, stores the return information for subroutines, function calls, and exceptions. In assembly language, the "bl" command places the program counter (PC) value into the LR.

R15 serves as the Program Counter (PC), containing the current program address. Upon reset, the processor loads the PC with the address of the reset vector.

The Program Status Register (PSR) is subdivided into the Application PSR (APSR), the Interrupt PSR (IPSR), and the Execution PSR (EPSR). The APSR holds the current state of the condition flags from previous instruction executions. The IPSR indicates the exception type number of the current interrupt service routine (ISR). The EPSR contains the Thumb state bit; if it is "0," the ARM instruction set is used, and if it is "1," the Thumb instruction set is utilized.

All of the aforementioned registers are classified as non-memory mapped registers; they are internal to the processor core and cannot be accessed from a C program. However, they can be accessed via assembly code.

Memory-mapped registers pertain to processor-specific peripherals (such as NVIC, MPU, SCB, DEBUG, etc.) and microcontroller-specific peripherals (such as RTC, I2C, TIMER, CAN, USB, etc.). Each register has a unique address, allowing access from C code.

Picture Source: Cortex-M4 Technical Reference Manual - Revision r0p0

Written By: Musaab Taha 

What are the different access level of Arm Cortex-M0/3/4 Processor ?

 The Arm Cortex-M0/3/4 Processor has 2 access levels

1 - Privileged Access Level (PAL)

2 - Non-Privileged Access Level (NPAL)

In Privileged Access Level, the code to be executed has full access to all of the processor resources. In Non-Privileged Access Level, the code has restricted access to the processor resources and registers. By default, the code will run in Privileged Access Level. When the processor is in 'Thread Mode', it is possible to move the processor to Non-Privileged Access Level, but it is not possible to go back to the Privileged Access Level unless it changes first to handler mode. The access level of the 'Handler Mode' is always Privileged Access Level. Switching between Privileged Access Level and Non-Privileged Access Level can be done using the processor control register.

Written By: Musaab Taha 

What are the different operational modes of Arm Cortex-M0/3/4 Processor ?

The Arm Cortex-M0, M3 and M4 processor has two operational modes.

These modes include Thread mode, Handler mode. In Thread mode which also called as "User Mode", the processor executes application code either with or without access to the processor full resources, which also called as the access level, we are going to talk about the different access levels in a separate article. The handler mode is reserved for handling exceptions and interrupts, ensuring timely response to system events and it executes the ISR (Interrupt Service Routine) with the access to the processor full resources . These operational modes empower developers to optimize performance, security, and resource utilization in embedded systems powered by Cortex-M0, M3, and M4 processors.

Written By: Musaab Taha 

How to implement printf in Stm32 Arm Cortex-M3/4/7 Microcontrollers

Using printf in STM32 ARM Cortex-M3/M4/M7 microcontrollers requires setting up a few things before you can start printing out messages. Firstly, you need to configure the ITM (Instrumentaton Trace Macrocell) unit to send its FIFO buffer content through the SWO (Serial Wire Output) pin of the SWD (Serial Wire Debug) Interface. This can be done by the follwoing code:

//Debug Exception and Monitor Control Register base address

#define DEMCR        *((volatile uint32_t*) 0xE000EDFCU )

/* ITM register addresses */

#define ITM_STIMULUS_PORT0    *((volatile uint32_t*) 0xE0000000 )

#define ITM_TRACE_EN          *((volatile uint32_t*) 0xE0000E00 )

void ITM_SendChar(uint8_t ch)

{

//Enable TRCENA

DEMCR |= ( 1 << 24);

//enable stimulus port 0

ITM_TRACE_EN |= ( 1 << 0);

// read FIFO status in bit [0]:

while(!(ITM_STIMULUS_PORT0 & 1));

//Write to ITM stimulus port0

ITM_STIMULUS_PORT0 = ch;

}

And by changing the write function in the syscalls.c source file as follows:

__attribute__((weak)) int _write(int file, char *ptr, int len)

{

(void)file;

int DataIdx;

for (DataIdx = 0; DataIdx < len; DataIdx++)

{

//__io_putchar(*ptr++);

ITM_SendChar(*ptr++);

}

return len;

}

In the STM32cubeide the SWV(Serial Wire Viewer) will then receive the printf statements and

display it in the console. In the SWV ITM Data Console, set the ITM Stimulus Port to '0',

and before running the application press on 'start trace'. As can be seen on the following

picture.

With these steps in place, you can easily utilize printf for debugging and communication purposes in your STM32 ARM Cortex-M3/M4/M7 projects.

Link to the code in github: https://github.com/MusaabTaha/STM32-ARM-Cortex-M4-Microcontroller-Codes/blob/main/helloworld.c

Written By: Musaab Taha

Why Cortex-M Family of Processors ?

The Cortex-M family of processors, especially the ARM Cortex-M3/M4, is a captivating choice for anyone looking to delve into embedded systems. What makes it so appealing? Well, for starters, it's incredibly budget-friendly, which means more people can get their hands on it and start tinkering. Plus, it's lightning-fast and super efficient, meaning you can do a lot without draining your battery too quickly. And let's talk about code—this thing squeezes every last drop of performance out of your memory, which is pretty darn cool. Oh, and interrupt management? It's top-notch, making sure your device stays responsive even when things get hectic. There's a whole bunch of other perks too, but suffice it to say, jumping into ARM Cortex-M3/M4 development is like opening a door to a world of exciting possibilities.

Written By: Musaab Taha