The Arm Cortex-M4 registers are integral components located within the processor core. It comprises 13 general-purpose registers, R0 through R12. All core registers are 32-bit wide. The stack pointer (SP) is further divided into the Process Stack Pointer (PSP) and the Main Stack Pointer (MSP) based on the processor's active mode. The Link Register (LR), R14, stores the return information for subroutines, function calls, and exceptions. In assembly language, the "bl" command places the program counter (PC) value into the LR.
R15 serves as the Program Counter (PC), containing the current program address. Upon reset, the processor loads the PC with the address of the reset vector.
The Program Status Register (PSR) is subdivided into the Application PSR (APSR), the Interrupt PSR (IPSR), and the Execution PSR (EPSR). The APSR holds the current state of the condition flags from previous instruction executions. The IPSR indicates the exception type number of the current interrupt service routine (ISR). The EPSR contains the Thumb state bit; if it is "0," the ARM instruction set is used, and if it is "1," the Thumb instruction set is utilized.
All of the aforementioned registers are classified as non-memory mapped registers; they are internal to the processor core and cannot be accessed from a C program. However, they can be accessed via assembly code.
Memory-mapped registers pertain to processor-specific peripherals (such as NVIC, MPU, SCB, DEBUG, etc.) and microcontroller-specific peripherals (such as RTC, I2C, TIMER, CAN, USB, etc.). Each register has a unique address, allowing access from C code.
Picture Source: Cortex-M4 Technical Reference Manual - Revision r0p0
Written By: Musaab Taha
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